/*
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Lei Zhang
 */

#ifndef __ARCH_UNICORE_INSTS_STATICINST_HH__
#define __ARCH_UNICORE_INSTS_STATICINST_HH__

#include "base/trace.hh"
#include "cpu/static_inst.hh"

namespace UnicoreISA
{

class UnicoreStaticInst : public StaticInst
{
  protected:

      // condition field (needed by bcc and cmov/cnot)
      uint32_t bc;

    // Constructor
    UnicoreStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
        : StaticInst(mnem, _machInst, __opClass)
    {
    }

    /// Print a register name for disassembly given the unique
    /// dependence tag number (FP or int).
    void
    printReg(std::ostream &os, int reg) const;

    std::string
    generateDisassembly(Addr pc, const SymbolTable *symtab) const;

    void
    advancePC(UnicoreISA::PCState &pcState) const
    {
        pcState.advance();
    }

    // stone: copied from ARM
    template<class XC>
    static inline Addr
    readPC(XC *xc) { 
        // NOTE: when we read PC, it's the real PC
        return xc->pcState().pc();
    }

    inline std::string getCondStr() const {
	    std::string str_cond; 
	    switch(bc) {
	        case 0:
	            str_cond = "eq";
	            break;
	        case 1:
	            str_cond = "ne";
	            break;
	        case 2:
	            str_cond = "ea";
	            break;
	        case 3:
	            str_cond = "ub";
	            break;
	        case 4:
	            str_cond = "fs";
	            break;
	        case 5:
	            str_cond = "ns";
	            break;
	        case 6:
	            str_cond = "fv";
	            break;
	        case 7:
	            str_cond = "nv";
	            break;
	        case 8:
	            str_cond = "ua";
	            break;
	        case 9:
	            str_cond = "eb";
	            break;
	        case 10:
	            str_cond = "eg";
	            break;
	        case 11:
	            str_cond = "sl";
	            break;
	        case 12:
	            str_cond = "sg";
	            break;
	        case 13:
	            str_cond = "el";
	            break;
	        default:
	            str_cond = "cc";
	            break;
	    }
	    return str_cond;
	}

	inline bool afrOk(uint8_t afr) const
	{
	    uint8_t ov = afr & 1,
	            ca = (afr >> 1) & 1,
	            ze = (afr >> 2) & 1,
	            sn = (afr >> 3) & 1;
	    switch (bc) {
	        case 0:
	            return ze == 1;
	        case 1:
	            return ze == 0;
	        case 2:
	            return ca == 1;
	        case 3:
	            return ca == 0;
	        case 4:
	            return sn == 1;
	        case 5:
	            return sn == 0;
	        case 6:
	            return ov == 1;
	        case 7:
	            return ov == 0;
	        case 8:
	            return (ca == 1 && ze == 0);
	        case 9:
	            return (ca == 0 || ze == 1);
	        case 10:
	            return sn == ov;
	        case 11:
	            return !(sn == ov);
	        case 12:
	            return (ze == 0 && sn == ov);
	        case 13:
	            return (ze == 1 || !(sn == ov));
	        case 14:
	            return true;
	        default:
	            return false;
	    } 
	}

};

} // namespace UnicoreISA

#endif //__ARCH_UNICORE_INSTS_STATICINST_HH__
